Experimental and Modeling Studies on Solder Self-alignment for Optoelectronic Packaging

Kong, Ming

Graduate Thesis Or Dissertation

Experimental and Modeling Studies on Solder Self-alignment for Optoelectronic Packaging Public Deposited

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Citeable URL: https://scholar.colorado.edu/concern/graduate_thesis_or_dissertations/cr56n1249

Abstract

Solder self-aligning technology is important to the manufacturing of cost-effective optoelectronic modules requiring accurate alignments. This thesis is to understand major effects on self-alignment accuracies in order to establish a model to guide the design for precision solder self-alignments. A solder self-alignment model based on force optimization with six degrees of freedom in a static configuration has been developed to predict an alignment accuracy with respect to different manufacturing parameters and variations. The model was used to design a VCSEL (vertical cavity surface emitting laser) array soldered on a substrate. It was proven to be a powerful tool for the design of optoelectronic modules. For example, when using Ø80 µm solder spheres with 2 µm diameter variation to attach a VCSEL chip (3200 µm × 500 µm × 650 µm) on a substrate, the model shows that the chip's standoff height variation could be reduced from 5.6 to 2.0 µm by adding extra alignment pads. Solder insufficient wetting on the bonding pads was identified to be the most undesirable factor affecting self-alignment accuracy. It could result in a planar misalignment from several to tens of µms depending on wetting quality and design parameters. Solder void was another undesirable factor that could increase the average standoff height of the assembled unit by 4 to 10 µms in the cases studied. Other factors, e.g. manufacturing variations in pad position and diameter, chip/substrate warpage, small tilt of the reflow stage, could only account for less than ±1 µm misalignments. The accuracy of the solder self-alignment model was verified by experimental characterizations using 3 mm × 3 mm glass-on-silicon flip-chip test vehicles comprising 25 solder joints. In addition to static cases, solder self-alignments in a dynamic condition was studied. The vibration of the substrate near the resonant frequencies could cause large chip-to-substrate misalignments. The resonant motion could be "frozen in" during the solidification of the reflow process and resulted in large misalignments. For a 25 mm × 25 mm ball grid array test vehicle reflowed under a horizontal vibration at 12 Hz and less than 2 µm amplitude, the chip-to-substrate lateral misalignments could reach beyond 100 µm due to the resonance effect. For any real applications, it is important to characterize the frequency range of the manufacturing environment and make sure the resonant frequencies of the assembly are far from the range.

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