Date of Award
Doctor of Philosophy (PhD)
Y. C. Lee
Nanowires (NWs) have attracted considerable interests in many applications due to their small size, extremely high surface-to-volume ratio, and superior material properties. They are promising material candidates as fundamental building blocks for future electronic, optoelectronic, energy, sensor, and biomedical applications. The majority of research activities have focused on the synthesis of NWs. With the advent of high-performance NWs, interconnect and packaging of NWs are becoming increasingly important for device applications. Vertical NW array devices, compared with horizontal NW configurations, are of great importance for achieving ultra-high integration density at the device level without the need of additional assembly and rearrangement processes. Currently, however, it is very challenging to interconnect and package as-grown vertical NWs because of their small sizes and extremely high aspect ratios. This thesis work contributes to the design, fabrication, and characterization of atomic layer deposition (ALD)-enabled interconnect and packaging technologies for as-grown vertical NWs. The first goal of this thesis is to develop a generic interconnect technology that can interconnect and encapsulate as-grown vertical NWs. We have developed a novel interconnect solution by encapsulating as-grown NWs with a nanoscale multilayer consisting of ALD-alumina and tungsten (W) layers for dielectric and electrical interconnects. The electrical connection of ALD-enabled interconnect was verified by the photoluminescence (PL) measurement of NWs. By injecting current into W interconnect along NWs, a dynamic PL tuning experiment was demonstrated, and this experiment verified the connection of W interconnect on NWs. The effect of the matrix layer on PL measurement has been studied and a process has been developed to eliminate such an effect. With local removal of ALD-W at the tips of the NWs, we verified that the PL is measured from the tip of the NWs. By measuring temperature dependence of peak PL wavelength from the tips of the NWs, we are able to predict tip temperature and corresponding thermal performance of as-grown NW devices. With the increase of device integration density and power consumption in electronics and optoelectronics, thermal management is one of the most critical packaging issues. A much higher power density than that in conventional planar devices is expected for as-grown vertical NW devices due to the potentially much high integration density. The second goal of this thesis is thus devoted to developing an effective cooling design and fabrication for as-grown NW devices. Thermal simulation is used to guide the design and fabrication of cooling-enhanced as-grown NW devices. NWs are successfully encapsulated with adjustable-thickness coverage of electroplated copper as effective heat spreading. Thermal simulation predicts a reduction of thermal resistance by 52X for the electroplated copper on as-grown NW devices compared with state-of-the-art polymer encapsulation.
Cheng, Jen-Hau, "Atomic Layer Deposition Enabled Interconnect and Packaging Technologies for As-Grown Nanowire Devices" (2010). Mechanical Engineering Graduate Theses & Dissertations. 14.