Date of Award

Spring 1-1-2018

Document Type


Degree Name

Doctor of Philosophy (PhD)

First Advisor

Khurram Khan. Afridi

Second Advisor

Dragan Maksimovic

Third Advisor

Robert W. Erickson

Fourth Advisor

Hanh-Phuc Le

Fifth Advisor

Daniel Costinett


Due to the ever decreasing thickness and increasing battery size of modern cellphones, battery chargers inside cellphones are required to meet increasingly stringent power density requirements, including small printed circuit board (PCB) area and component height. This thesis is focused on low-profile, high-power-density, and high-efficiency dc-dc converters for battery charging applications.

This thesis investigates five topologies, including ZVS-QSW buck converter, three-level buck converter, four-level buck converter, a resonant switched capacitor converter, and a new reconfigurable hybrid switched capacitor converter. The operation principle of each topology is described, and the advantages and disadvantages of each topology are analyzed and compared in terms of efficiency and power density. To accurately evaluate the performance of each topology, this thesis utilizes the augmented state-space modeling method that efficiently calculates the steady-state waveforms of a converter. To accurately predict losses, the dynamic on-resistance of GaN transistors and core loss of inductors have been modeled. Furthermore, a comprehensive optimization methodology is utilized to select circuit and component parameters.

For 2:1 conversation ratio application scenario, two prototypes using GaN transistors and low-voltage Silicon MOSFET have been designed, built and tested for an input voltage range of 5 V to 20 V, an output voltage range of 3 V to 4.2 V, and a maximum output current of 10 A. The prototype with GaN transistors (EPC2023) occupies a PCB area of 358 mm2 with component height of 1 mm. To maximize efficiency, the converter is designed to achieve ZVS at light-to-medium loads, while sacrificing ZVS to reduce transistor conduction and inductor losses. This prototype converter achieves a peak efficiency of 98.5%. The prototype using low-voltage Silicon MOSFET (CPF03433) occupies a PCB area of 310 mm2. A prototype of four-level buck converter with a PCB area of 410 mm2, optimized for 3:1 conversion ratio, has also been built and tested. For extreme-power-density application, a prototype with a PCB area of 79.6 mm2 and component height of 1 mm is built and tested. The prototype converter achieves a peak efficiency of 96.7% and a power density of 3230 W/in3.