Date of Award

Spring 1-1-2015

Document Type


Degree Name

Doctor of Philosophy (PhD)


Electrical, Computer & Energy Engineering

First Advisor

Bart Van Zeghbroeck

Second Advisor

Thomas Schibli

Third Advisor

Garret Moddel

Fourth Advisor

Won Park

Fifth Advisor

Juliet Gopinath


In this thesis we explore the potential of versatile graphene-semiconductor heterojunctions in photodetection and field-effect transistor (FET) applications. The first part of the thesis studies near-infrared photodiode (NIR PD) based on a graphene- n-Si heterojunction in which graphene is used as the absorbing medium. Graphene is chosen for its absorption in NIR wavelengths to which Si is not responsive. Most graphene detectors in the literature are photoconductors that have a high dark current. The graphene-Si heterojunction PD has a large Schottky barrier height that suppresses the dark current and enhances the current rectification and the photon detectivity.

The fabricated graphene-Si heterojunction PD under conventional telecommunication 1.3 (1.5)-μm illumination exhibits a responsivity of 3 (0.2) mA/W, an internal quantum efficiency of 14 (0.6) %, a noise-equivalent power of 1.5 (30) pW/Hz0.5, and a specific detectivity of 3 (0.1)x109 cm Hz0.5/W. An unexpected tunnel oxide is observed at the graphene-Si interface, further reducing the dark current. The performance in terms of sensitivity and noise is comparable to the commercially available discrete germanium NIR PDs due to its low dark current density on the order of 10 fA/μm2. The Si CMOS-compatible PD based on graphene-Si heterojunction provides a promising route to realize a critical component for monolithically integrated Si photonic interconnects.

The second part of the thesis focuses on a novel graphene junction FET (GJFET) gated by a graphene-semiconductor heterojunction. The majority of graphene transistors in the literature -- including MOSFETs, barristors, and tunneling FETs -- have a heavily-doped Si back gate separated from the graphene channel by a conventional or high-K dielectric layer. The threshold voltage of individual transistors cannot be tuned easily in such designs, and have an additional problem with shorted back gates. In GJFETs, a Schottky junction is formed as graphene is placed on a semi conductor, resulting in a depletion region inside the semiconductor that induces a complementary charge in the graphene. Changing the reverse bias across the graphene-semiconductor junction modulates the depletion region width and thereby changes the total charge in graphene. The charge density of the graphene is also modulated by the doping density of the semiconductor substrate. The GJFET structure provides a solution for Dirac voltage tuning and back gate isolation by location-specific doping on a single device wafer.

A detailed understanding of the device is obtained through the design, fabrication, and analysis of GJFETs with atmospheric pressure chemical-vapor deposited graphene on n-type Si and 4H-SiC substrates of various doping densities. A variable depletion width model is built to numerically simulate the performance. A representative n-Si (4.5x1015 cm-3) GJFET exhibits an on-off ratio of 3.8, an intrinsic hole density of 8x1011 cm-2, and a Dirac voltage of 14.1 V. Fitting the transfer characteristic of the Si GJFET with our device model yields an electron and hole mobility of 300 and 1300 cm2/V s respectively. The tunability of the threshold voltage by varying the substrate doping density is also demonstrated. With an increasing substrate doping from 8x1014 to 2x1016 cm-3, the threshold of the Si GJFET decreases from 24.9 V to 3.8 V. With even higher doping density (5x1018 cm-3) in n+-4H-SiC, the Dirac voltage of the GJFET is further reduced to 1.5 V. These results also demonstrate the feasibility of integrating GJFET with semiconductor substrates other than Si, widening their potential for use in high-frequency electronics.